Clockless farmost toggle flip-flop circuit

ABSTRACT

A clockless, ratioless IGFET toggle flip-flop is composed of a FARMOST inverter whose input and output are bridged by the series-connected source-drain circuits of a pair of switching transistors. The gates of the switching transistors are connected, respectively, to the true rail and the complement rail of a double-rail trigger signal source. The true rail is also connected to the clock input of the FARMOST inverter, and the flip-flop output is taken between the two switching transistors. The operation of the circuit involves the transfer of incremental charges between the inverter output capacitance, the flip-flop circuit output capacitance, and the gate capacitance of the inverter input transistor.

United States Patent Christensen [45] Feb. 15, 1972 [54] CLOCKLESS FARMOST TOGGLE FLIP- 3,483,400 12/ I969 Washizuka et all ..307/25l X FLOP CIRCUIT Primary Examiner-John S. Heyman [72] Inventor: AIM Q. Chm, HOIJSiOn, Tex. McCarthy and T E Bieber [73] Assi nee: Shell Oil Com New York, N.Y.

8 57 ABSTRACT [22] Filed: Mir. 24, 1970 A clockless, ratioless IGFET toggle flip-flop is composed of a PP 22,194 FARMOST inverter whose input and output are bridged by the series-connected source-drain circuits of a pair of I52] Lsv C I 307/279 switching transistors. The gates of the switching transistors are i 5 H connected, respectively, to the true rail and the complement 58 re rail of a double-rail trigger signal source. The true rail is also I l I Search 307/205 304 connected to the clock input of the FARMOS'I inverter, and I 56] References Citd the flip-flop output is taken between the two switching transistors. The operation of the circuit involves the transfer UNITED STATES PATENTS of incremental charges between the inverter output capacitance, the flip-flop circuit output capacitance, and the g: 35 azi l ig gate capacitance of the inverter input transistor. 3,431,433 3/1969 Ballet al. ............:.........II:3o7/251 x 2Claims, ZDrawing Figures O OUTPUT PATENTEDFEB 15 me OUTPUT FIG. 2

INVENTOR.

ALTON O. CHRISTENSEN BY 6 64 Wwi/ ATTORNEYS CLOCKLESS F ARMOST TOGGLE FLIP-FLOP CIRCUIT BACKGROUND OF THE INVENTION lfiled May 18, 1970 and entitled Ratioless Flip-Flop.

Prior art circuits of this type, however, have required a separate supply of clock pulses in addition to the triggenpulses and have required as many as ten elements (such as IGFETS or diodes) to carry out their function. With speed, small area, and low power consumption being essential attributes of MOS (circuitry, the prior artdevices were consequently relatively inefficient.

SUMMARY OF THE INVENTION The circuit of this invention provides a greatlysimplified perior to prior art circuits of the same type in respect to size,

speed of operation, and power consumptionThe device of this invention has the superior speed characteristics of a ratioless arrangement, and its power requirements are reduced both by the reduction in the number of devices to beoperated andby the elimination of the need for a separate clockpulse supply.

Essentially, the flip-flop of this invention consists of a FAR- MOST (Fast Acting Ratioless Metal Oxide Silicon-Transistor) inverter whose gate and output are connected by the series- Y connected source-drain circuits of a pair of lGFETs. The gate electrodes of these lGFETs are connected, respectively, to a dual-rail trigger signal source, Le, a source providingboth a trigger signal T and an inverted trigger signal T. The trigger signal is also applied to the clock input of the FARMOST intoggle flip-flop circuit for MOS circuitry which is markedly suthe FARMOST inverter through the series-connected sourcedrain circuits of switching transistors 20, 22.

The output of the flip-flop circuit is taken at the junction 24 between the source-drain circuits of the switching transistors 20, 22. It will be understood that the flip-flop output has an in herent flip-flop output capacitance 26 which may be the line capacitance of the flip-flop output line, the gate capacitance of the gate electrode ofthe next following stage, or a combination of both. In any event, it is essential that the total flip-flop output capacitance 26 be larger than the gate capacitance of the gate electrode 18.

The operation of the circuit is as follows:

During the first trigger pulse on the true rail T of the doublerail trigger pulse source, the inverter output capacitance I6 is precharged through the diode I2. At the end of the trigger pulse, T returns to ground, the complement rail T of the double rail trigger pulse source becomes energized and causes a portion of the charge on the inverter output capacitance 16 to be transferred to the flip-flop output capacitance 26. Consequently, if sufficient charge is transferred to bring the flipflop output capacitance 26 above threshold level V,,,, the flipflop output will be at logic l following the first trigger pulse.

When the next trigger pulse occurs, switching transistor 22 is blocked and switching transistor 20 is enabled by the trigger pulse T. As a result, the negative charge on the flip-flop output capacitance 26 is transmitted through switching transistor 20 to the gate electrode 18 of the inverter transistor 14.

Upon the cessation of the second trigger pulse, the switching transistor 20 is blocked, thus maintaining the inverter transistor 14 in an enabled condition. At the same time, switching transistor 22 is enabled, and the charge on tee flip flop output capacitance 26 drains off to ground through switching transistor 22 and inverter transistor 14. Simultane- 1 verter, and the output of the flip-flop is taken at the junction of theseries-connected IGFET source'drain circuits The operation of the circuit involvesa transfer of energy between the line capacitance of theoutput line of the 'FARMOST invertenthe gate capacitance-of the FARMOSTinverter, and the output capacitance of the circuit, the latter being the largest'of thethree.

It is therefore theobjectof the invention to provide a simplified toggle flip-flop circuit for capacitive loads using a T signal and a T signal as the sole inputs.

It is another object of this invention to accomplish the above result by providing a FARMOST inverter whose; gate and output terminals are bridged by a pair of lGFETs whose source-drain circuitsare connected in series.

BRIEF DESCRIPTION OF THE DRAWINGS FIG; I shows a circuit diagram of a toggle flip-flop circuit in accordance with this invention;

FIG. 2 is a time-amplitude diagram showing the relation of various waveforms involved in the operation of the circuit of FIG. I.

DESCRIPTION OF THE PREFERRED EMBODIMENT As shown in FIG. 1, the circuit of this invention includes a FARMOST inverter 10 which may advantageously consist of a diode 12 (preferably a barrier-type diode such as a Shottky diode)-and an inverting transistor 14. The clock input of the FARMOST inverter 10 isconnected to the true rail of a double-rail source of trigger pulses, and its output feeds into an inverter output capacitance 16. The capacitance 16 may be the line capacitance of the inverter output line. The gate electrode I8 of the inverting transistor I4 is connected to the output of ously, the charge imparted to capacitance 16 by the second trigger pulse is drained off through inverter transistor 14.

Upon the occurrence of the third trigger pulse, the enabling of switching. transistor 20 causes the charge on the gate electrode 18 to be dissipated into the flip-flop output capacitance 26. It will be seen that the flip-flop output capacitance 26 must be substantially larger than the gate capacitance of gate electrode l8so that enough charge can dissipate from gate electrode 18 to drop the potential on gate electrode 18 below threshold.

After the cessation of the third trigger pulse, the circuit goes .through thesame function as after the first trigger pulse. The

, chargedumped into capacitance 26 from the gate capacitance charging of capacitance 26 from capacitance 16 by raising the initial charge level of capacitance 26 at the beginning of the charge transfer. The cycle will then repeat. It will be noted that the output changes state following the end of each pulse,

and that its state will alternate between logic 0" and logic An advantageous feature of the circuit of this invention is the fact that the spacing between trigger pulses is immaterial to the functioning of the circuit. Once the flip-flop output capacitance ,26 has been discharged into the grounded T supply through switching transistor 22 and inverted transistor 14 following the end of an even-numbered trigger pulse, the charge on the gate electrode l8 has fulfilled its purpose, and it does not matter if this charge leaks off during a long interval between trigger pulses. Consequently, the clockless nature of .the circuit of this invention provides a considerable saving in and a reference potentiah'the source-drain circuit of the inverter lGFET means and the capacitive means being connected in series and across the clock input;

. a flip-flop output, second capacitive means provided between the flip-flop output and reference potential; I first switching lGFET means having a source-drain circuit connected between said inverter output and said flip-flop output, and a gate electrode connected to the complement rail of said double-rail trigger pulse source; and

e; second switching IGF ET means having a source-drain cir- 

1. A clockless, ratioless IGFET toggle flip-flop circuit, comprising: a. A double-rail source of complementary trigger pulses; b. ratioless IGFET inverter means having a clock input connected to the true rail of said double-rail trigger pulse source, inverter IGFET means, and an inverter output, capacitive means provided between the inverter output and a reference potential, the source-drain circuit of the inverter IGFET means and the capacitive means being connected in series and across the clock input; c. a flip-flop output, second capacitive means provided between the flip-flop output and reference potential; d. first switching IGFET means having a source-drain circuit connected between said inverter output and said flip-flop output, and a gate electrode connected to the complement rail of said double-rail trigger pulse source; and e. second switching IGFET means having a source-drain circuit connected between the gate electrode of said inverter IGFET means and said flip-flop output, and a gate electrode connected to said true rail of said double-rail trigger pulse source.
 2. The flip-flop circuit of claim 1, in which said flip-flop output coupling capacitance is substantially larger than the gate electrode capacitance of said inverter IGFET. 